1. Field of the Invention
The present invention generally relates to phase adjustment techniques, and in particular to a phase adjustment system and method for a phase shifter.
2. Description of the Related Art
There has been proposed an endless phase shifter (hereinafter abbreviated as EPS) having a read-only memory (ROM) used as a non-linear converter in Japanese Patent Application Unexamined Publication No. H05-55873. More specifically, the ROM stores sine wave data, which is read out depending on a given address signal. The EPS is provided with an accumulator storing phase data, which is used as an address signal to read sine wave data from the ROM. Accordingly, by converting the read sine wave data from digital to analog, the analog sine wave signal whose phase is controlled depending on the phase data can be obtained. It is supplied as a local oscillation signal to a mixer to produce an output signal having a phase thereof also controlled depending on the phase data.
As another prior art, a correction data generator for a multi-level and multi-phase modulator has been proposed by the Inventor (see Japanese Patent Application Unexamined Publication No. H01-133452). According to the correction data generator, when the modulator is provided with reference data for each of the multi-level points, the phase and amplitude of an output of the modulator are measured and compared with the reference data to produce correction data. The correction data is updated until the measured phase and amplitude data are within the specifications. The final correction data for each multi-level point is written into a ROM by a ROM writer. The ROM storing the above correction data is mounted in the modulator and thereafter verification is performed to check whether the modulator produces a precise modulation vector.
However, such a ROM needs a considerably large connection space or a hole, causing a problem about space saving. Especially, a high-frequency circuit such as an EPS is susceptible to such a space or hole, which may cause deteriorated characteristics of modulation, resulting in more difficult circuit design.
Recently, the trend has been for the capacity of a ROM to increase more and more and a relatively small-capacity ROM to be dropped from production. However, the above-described correction data can be stored in only a small-capacity ROM without the need of a large-capacity ROM. Therefore, if a large-capacity ROM must be used, undesired cost is increased.
Further, in the case of a correction data storing ROM, it is not easy to adjust and write correction data onto the ROM.
An object of the present invention is to provide an adjustment system and method which can achieve a downsized endless phase shifter without decreasing in phase shift characteristics.
Another object of the present invention is to provide a system and method allowing easy adjustment of a phase shifter.
According to an aspect of the present invention, an endless phase shifter includes: a phase shifter for shifting a phase of an output signal depending on a phase control signal; and a programmable logic device (PLD) connected to the phase shifter, for correcting a standard vector depending on correction data to output a corrected vector as the phase control signal to the phase shifter, wherein the correction phase is written into the PLD through a download connector connected to a computer.
According to another aspect of the present invention, a system for adjusting a phase shifter includes: a programmable logic device (PLD) connected to the phase shifter, for correcting a standard vector depending on correction data written thereto; an analyzer for supplying a standard input signal to the phase shifter and analyzing an output signal of the phase shifter to measure phase and amplitude of the output signal; and a processor for generating a standard vector for a sequentially selected one of a plurality of phase points to output it to the phase shifter, calculating correction data for a selected phase point based on the measured phase and amplitude obtained by the analyzer, and generating a writer for writing correction data for all the phase points into the programmable logic device.
The processor may write predetermined data in the PLD to set the PLD for a through state where the standard vector passes through the PLD to the phase shifter. The standard vector may be transferred from the processor to the PLD through a download connector. The writer may be a data writing program which is automatically generated depending on the correction data for all the phase points. The data writing program may be described in a hardware description language (HDL).
The processor may calculate correction data for each of a plurality of previously selected phase points and then calculates correction data for all the phase points by estimating correction data for phase points positioned between adjacent ones of the selected phase points using interpolation.
According to further another aspect of the present invention, a method for adjusting a phase shifter includes the steps of: a) providing the phase shifter with a standard vector for a sequentially selected one of a plurality of phase points; b) analyzing an output signal of the phase shifter to measure phase and amplitude of the output signal with respect to an input standard signal; c) calculating correction data for a selected phase point based on the measured phase and amplitude; d) storing correction data for all the phase points; and e) writing the correction data in a programmable logic device (PLD) so as to provide the phase shifter with a corrected vector for each of the phase points.
The step (c) may include the steps of: c.1) determining whether the measured phase and amplitude fall into a predetermined range; c.2) when the measured phase and amplitude fall out of the predetermined range, generating an updated vector by changing the standard vector based on errors between the measured phase and amplitude and the predetermined range; c.3) providing the phase shifter with the updated vector; c.4) repeating the steps (b), (c.1), (c.2), and (c.3) until the measured phase and amplitude fall into the predetermined range; c.5) when the measured phase and amplitude fall into the predetermined range, calculating correction data based on the updated vector and the standard vector.
The step (c) may further include the step of: c.6) calculating correction data for phase points positioned between adjacent ones of the selected phase points using interpolation.
The step (e) may include the steps of: e.1) automatically generating a data writing program depending on the correction data for all the phase points; and e.2) writing the correction data in the programmable logic device (PLD) by executing the data writing program.